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digital controller for isolated power supply with pmbus inter f ace preliminary technical data adp105 1 rev. pra information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. specifications subject to change without notice. no license is granted by implication or otherwise under any patent or paten t rights of analog devices. trademarks and registered trademarks are the property of their respective owners. one technology way, p.o. box 9106, norwood, ma 02062 - 9106, u.s.a. tel: 781.329.4700 www.analog.com fax: 781.461.3113 ? 2013 analog devices, inc. all rights reserved. features versatile, digital voltage mode controller high speed, input voltage feed - forward control 6 pwm logic outputs with 625ps resolution switching frequency 50 khz to 625 khz frequency synchronization master & slave multiple energy saving modes adaptive dead - time compensation for efficiency optimization low device power consumption - typical 100 mw direct parallel operation ? accurate droop current share ? pre - bias start - up ? rev erse current protection ? conditional over - voltage protection extensive fault detection and protections ultra compact package design 4*4mm 24 - pin lfcsp pmbus compliant easy to use programming via graphic user interface (gui) high reliability eeprom for programming & data storage - 40 c ~ 125 c operation temperature applications high density, isolated dc/dc power supplies ? intermediate bus converters ? high availability parallel power systems server, storage, industrial, networking, and communications infrastructure general description the adp1051 is an advanced digital controller with pmbus tm interface targeting high density, high efficiency dcdc power conversion. this control ler implements voltage mode control with high speed , input line feed - forward for enhanced transient and improved noise performance. the adp1051 has 6 programmable pwm outputs capable of controlling most high ef ficiency power supply topologies with added control of synchronous rectification. the device includes adaptive dead - time compensation to improve the efficiency over the load range and programmable light load mode operation combined with low device power co nsumption to reduce system standby power losses. the adp1051 implements several features to enable a robust system of parallel and redundant operation for customers that require high availability or parallel co nnection. the device includes master/slave synchronization, reverse current protection and pre - bias start - up, accurate current sharing between power supplies and conditional overvoltage techniques to identify and safely shutdown an erroneous power supply i n parallel operation mode. the adp1051 is based on flexible state machine architecture and is register programmed using an intuitive, graphical - user interface. the easy Cto - use interface reduces design cycle ti me and results in a robust, hardware coded system loaded in to the built - in eeprom. the small size 4*4 mm lfcsp package makes the adp1051 ideal for ultra - compact, isolated dcdc power module or embedded designs. figure 1 . typical application circuit icoupler dc input adp1051 outa outb load agnd res add rtd vcore ctrl cs1 vs- vs+ vdd ovp sda scl syni/flgi sr1 sr2 pg/alt# driver outc outd vf cs2- cs2+ driver pmbus
adp1051 preliminary technical data rev. pra | page 2 of 17 table of contents features ..................................................................................................... 1 applications .............................................................................................. 1 general description ................................................................................ 1 specifications ............................................................................................ 3 absolute maximum ratings .................................................................. 8 thermal resistance ............................................................................. 8 soldering .............................................................................................. 8 esd caution ......................................................................................... 8 pin configuration and function descriptions .................................... 9 a pplication configurations .................................................................. 11 typical performance characteristics .................................................. 13 theory of operation ............................................................................. 14 outline dimensions .............................................................................. 15 ordering guide .................................................................................. 15
preliminary technical data adp1051 rev. pra | page 3 of 17 specifications v dd = 3.0v to 3.6 v, t a = - 40c to + 12 5c, unless otherwise noted. fsr = full scale range. table 1 . specifications parameter symbol test conditions/comments min typ max unit supply v dd v dd 3. 0 3.3 3.6 v i dd i dd pwm pins unloaded normal operation (pson is high or low) 29 ma shut down (vdd below uvlo) 60 100 a during eeprom programming , 40 ms i dd + 6 ma power - on reset power - on reset v dd rising 3.0 v uvlo threshold v dd falling 2.750 2.850 2.975 v uvlo hysteresis 35 mv ovlo threshold 3.7 3.9 4.1 v ovlo debounce when set to 2 s 2 s when set to 500 s 500 s vcore pin output voltage 330 nf capacitor between vcore to agnd 2.50 2.6 2.70 v oscillator and pll pll frequency using res = 10 k? ( 0.1%) 190 200 210 mhz dpwm resolution 625 ps out a , out b , out c , out d, sr1 , sr2 pins output low voltage v ol sinking current = 10 ma 0.4 v output high voltage v oh sourcing current = 10 ma v dd ?0.4 v rise time c load = 50 pf 3.5 ns fall time c load = 50 pf 1.5 ns vs voltage sense pin input voltage range differential voltage from vs+ to vs - 0 1 1. 60 v input voltage fsr 1.6 v vs accurate adc valid input voltage range 1.6 v adc clock frequency 1.56 mhz register update rate 100 hz resolution 12 bits measurement accuracy factory trimmed at 1.0 v from 0% to 100% of input voltage range ?10 +10 % fsr - 1 60 +1 60 mv from 10% to 90% of input voltage range ? 2 .5 + 2 .5 % fsr - 40 + 40 mv from 900 mv to 1.1 v ? 1 .0 + 1 .0 % fsr - 16 + 16 mv temperature coeffient 65 ppm/ c common mode voltage offset - 200 +200 mv vs high speed adc equivalent sampling f sw khz
adp1051 preliminary technical data rev. pra | page 4 of 17 parameter symbol test conditions/comments min typ max unit frequency equivalent resolution at 390.6 khz switching frequency 6 bits dynamic range regulation voltage tbd mv to tbd v 25 mv vs uvp based on vs accurate adc uvp accuracy 1 4 % comparator update speed 82 us ovp pin usable voltage range 0.75 1.5 v threshold accuracy 1 1.25 % propagation delay (latency) debounce time not included 58 110 ns vf voltage sense pin input voltage range voltage from vf to agnd 0 1 1. 60 v input voltage fsr 1.6 v general adc valid input voltage range 1.6 v adc clock frequency 1.56 mhz register update rate 100 hz resolution 12 bits measurement accuracy from 10% to 90% of input voltage fsr ?3.5 +3.5 % fsr - 56 +56 mv from 0% to 100% of input voltage fsr ?10 +10 % fsr - 160 +160 mv feed forward adc input voltage range 0.5 1 1.6 v resolution 11 bits sampling period 10 s cs 1 current sense pin input voltage range v in d ifferential voltage from cs1 to agnd 0 1 1. 60 v input voltage fsr 1.6 v cs1 adc valid input voltage range 1.6 v adc clock frequency 1.56 mhz register update rate 100 hz resolution 12 bits measurement accuracy from 10% to 90% of input voltage range ? 3.5 +3.5 % fsr - 56 +5 6 mv from 0% to 100% of input voltage range ?10 +10 % fsr - 160 +1 60 mv cs1 fast ocp threshold value 1 1.18 1.2 1.22 v threshold value 2 0.22 0.25 0.28 v propagation delay (latency) debounce/blanking time not included 58 110 ns cs2 current sense pins input voltage range differential voltage from cs2+ to cs2? 0 120 mv input voltage fsr 120 mv common mode voltage to achieve measurement accuracy 0.9 1.15 1.4 v current sink (high side) 1.81 1.9 1.99 ma
preliminary technical data adp1051 rev. pra | page 5 of 17 parameter symbol test conditions/comments min typ max unit current source (low side) 4.99 k , 0.1% differential resistor 180 230 280 a temperature coefficient 70 ppm/c cs2 adc valid input voltage range 0 120 mv adc clock frequency 1.56 mhz resolution 12 bits measurement accuracy - 1 +1 mv low side mode with user trim from 0 mv to 110 mv ?1.85 +2.1 % fsr ?2.22 +2.52 mv from 110 mv to 120 mv ?6.1 +1.5 % fsr ?6.36 +0.84 mv high side mode with user trim from 0 mv to 110 mv ?1.6 +2.3 % fsr ?1.92 +2.76 mv from 110 mv to 120 mv ?5.3 +0.7 % fsr ?6.36 +0.84 mv cs2 accurate ocp threshold accuracy same as adc accuracy speed when set to 7 bits averaging speed 82 us when set to 9 bits averaging speed 328 us cs2 reverse current comparator threshold accuracy ? 3 mv setting - 8.5 ? 3.00 0 mv ? 6 mv setting - 12.0 ? 6 0 mv ? 9 mv setting - 15.5 ? 9 - 2.9 mv ? 12 mv setting - 18.5 ? 12 - 5.9 mv ? 15 mv setting ? 22.0 ? 15 ? 8.0 mv ? 18 mv setting ? 25.5 ? 18 ? 11.0 mv ? 21 mv setting ? 28.5 ? 21 - 14.0 mv ? 24 mv setting ? 32 ? 24 ? 16.5 mv threshold speed debounce = 40 ns 110 150 ns rtd temperature sense pin input voltage voltage from rtd to agnd 0 1.6 v input voltage fsr 1.6 v source current when set to 46 a, factory default setting 44.3 46 47.3 a when set to 40 a 38.6 40 42 a when set to 30 a 28.8 30 31.7 a when set to 20 a 18.8 20 21.5 a when set to 10 a 9.1 10 11 a rtd adc valid input voltage range 1.6 v adc clock frequency 1.56 mhz register update rate 100 hz resolution 12 bits measurement accuracy from 2% to 20% of valid input voltage ?0.3 +0.45 % fsr
adp1051 preliminary technical data rev. pra | page 6 of 17 parameter symbol test conditions/comments min typ max unit ?4.8 +7.2 mv from 0% to 100% of valid input voltage ?2.6 +1.6 % fsr otp threshold accuracy t = 85c with 100 k?||16.5 k? ?0.9 +0.25 % fsr ?14.4 +4 mv t = 100c with 100 k?||16.5 k? - 0.5 +1.1 % fsr - 8 +17.6 mv comparator speed 10 ms temperature readings according to internal linearization scheme factory trimmed to 46 a ( set register 0xfe2d to 0xe6); ntc r 0 = 100 k, 1%; beta = 4250 1%; r ext = 16.5 k 1% t = 25c to 100c 7 c t = 100c to 125c 5 c p g/alt# (open drain) pin output low level v ol sinking current = 10 ma 0.4 v ctrl, syni/flgi pins input low level v il sinking current = 10 ma 0.4 v input high level v ih v dd ? 0.8 v sda/scl pins v dd = 3.3 v input voltage low v il 0.8 v input voltage high v ih v dd ? 1.2 v output voltage low v ol 0.4 v leakage current ? 5 +5 a serial bus timing clock frequency 100 400 khz glitch immunity t sw 50 ns bus free time t buf 4.7 s start setup time t su;sta 4.7 s start hold time t hd;sta 4 s scl low time t low 4.7 s scl high time t high 4 s scl, sda rise time t r 1000 ns scl, sda fall time t f 300 ns data setup time t su;dat 250 ns data hold time t hd; dat 300 ns eeprom eeprom update time time from the updating command to eeprom updating finish (t j = 25c) 40 ms reliability endurance 1 t j = 85c 10,000 cycles t j = 12 5c 1 , 000 cycles data retention 2 t j = 85c 20 years t j = 12 5c 10 years 1 endurance is qualified as per jedec standard 22 method a117 and measured at ?40c, +25c, +85c, and +125c. 2 retention lifetime equivalent at junction temperature (t j ) = 85c as per jedec standard 22 method a117. retention lifetime derates with junc tion temperature.
preliminary technical data adp1051 rev. pra | page 7 of 17 figure 2 . serial bus timing diagram. 10241-003 scl sda p s t buf t hd;sta t hd;dat t high t su;dat t hd;sta t su;sta t su;sto t low t r t f s p
adp1051 preliminary technical data rev. pra | page 8 of 17 absolute maximum rat ings table 2 . absolute maximum rating parameter rating supply voltage (continuous) vdd 4.2 v digital pins: outa, outb, outc, outd, sr1, sr2, pg/alt#, sda, scl ?0.3 v to v dd + 0.3 v vs - to agnd ?0.3 v to +0.3 v vs, vf, ovp, rtd, add, cs1, cs2+, cs2 - ?0.3 v to v dd + 0.3 v syni/flgi, ctrl ?0.3 v to v dd + 0.3 v operating temperature range ?40c to +125c storage temperature range ?65c to +150c junction temperature 150 c peak solder reflow temperature snpb assemblies (10 to 30 secs) 240 c rohs compliant assemblies (20 to 40 secs) 260 c esd charged device model 1.5 kv esd human body model 5.0 kv stresses above those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. thermal resistance ja is specified for the worst - case conditions, that is, a device soldered in a circuit board for surface - mount packages. table 3 . thermal resistance package type ja jc unit 2 4 lead lfcsp 36.26 1.51 c/w soldering it is important to follow the correct guidelines when laying out the pcb footprint for the adp1051 , and for soldering the part onto the pcb. for detailed information about these guidelines, see the an - 772 application note . esd caution
preliminary technical data adp1051 rev. pra | page 9 of 17 pin configuration an d function descripti ons figure 3 . pin configuration table 4 . pin function descriptions pin no. mnemonic description 1 vs - inverting voltage sense input. this is the connection for the ground line of the power rail. there should be a low ohmic connection to agnd. it is recommended that the resistor divider on this input have a tolerance specification of 0.5% or better to allow for trimming. 2 vs+ noninverting voltage sense input. this signal is referred to vs?. it is recommended that t he resistor divider on this input h ave a tolerance specification of 0.5% or better to allow for trimming. 3 cs2 - inverting differential current sense input. nominal voltage at this pin should be 1.15 v for best operation. when using high - side current sensing in a 12 v application, place a 5.62 k resistor between the sense resistor and this pin. when using low - side current sensing, place a 5 k resistor betwe en the sense resistor and this pin. when using high - side current sensing, use the formula r = (v commonmode C 1.15)/1.9ma. a 0.1% resistor must be used to connect this circuit. 4 cs2+ noninverting differential current sense input. nominal voltage at this pin should be 1.15 v for best operation. when using high - side current sensing in a 12 v application, place a 5.62 k resistor between the sense resistor and this pin. when using low - side current sensing, place a 5 k resistor betwe en the sense resistor and this pin. when using high - side current sensing, use the formula r = (v commonmode C 1.15)/1.9 ma. a 0.1% resistor must be used to connect this circuit. 5 vf three optional functions can be implemented with this pin: feed forward, primary side input voltage sensing and input voltage lost detect . it is connected upstream of the output inductor through a resistor divider network. the nominal voltage at this pin should be 1v. this signal is referred to agn d 6 cs 1 primary side current sense input. this pin is connected to the primary side current sensing adc and to the fast ocp comparator. this signal is referred to a gnd. the resistors on this input must have a tolerance specification of 0.5% or better to a llow for trimming. 7 sr1 pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. 8 sr2 pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. 9 outa pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. 10 out b pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. 11 out c pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. this pin can also be programmed as a synchronization output. 12 out d pwm logic output drive. this pin can be disabled when not in use. this signal is referred to agnd. this pin can also be progra mmed as a synchronization output. 13 syn i/flgi synchronization signal i nput . it also used as a n external signal input to generate a flag condition. 14 scl i2c /pmbus serial clock input and output (open drain). this signal is referred to agnd. 15 sda i2c /pmbus serial data input and output (open drain). this signal is referred to agnd. 16 ctrl pmbus control signal. it is recommended that a 1 nf capacitor be included from the ctrl pin to agnd for noise debounce and decoupling. this signal is referred to agnd. 17 pg / a lt# power good output (open drain). this signal is referred to agnd. this pin is also used pmbus alert# signal. 18 vcore output of 2.6 v regulator. connect a minimum 330 nf decoupling capacitor from this pin to the agnd as close as poss ible to the ic, minimizing the pcb trace length. it is recommended that the vcore pin not be used as a reference or to generate other logic levels using resistive dividers. 19 vdd positive supply voltage 3.0 v to 3.6 v referred to agnd. connect a 2.2 f d ecoupling capacitor from this pin to the agnd as close as possible to the ic, minimizing the pcb trace length. adp1051 1 2 vs- vs+ ctrl ovp vf sr1 sr2 outa outb cs1 3 4 5 7 8 9 10 11 24 23 22 21 20 18 17 16 15 14 vdd pg/alt# syni/flgi sda scl agnd res rtd add vcore top view (not to scale) 6 12 outc outd 13 19 cs2- cs2+
adp1051 preliminary technical data rev. pra | page 10 of 17 pin no. mnemonic description 20 agnd ic common analog gnd. the internal analog circuitry ground and digital circuitry ground is star connected to this pin through bonding wires. 21 res resistor input. this pin sets up the internal reference for internal pll frequency. connect a 10 k resistor (0.1%) from res to agnd. this signal is referred to agnd. 22 add address select input to program i2c/pmbus address. connect a resistor from add to agnd. this signal is referred to agnd. 23 rtd thermistor input. place a thermistor 1 00 k 1% beta = 4250 1% in parallel with a 16.5 k? (1%) resistor. this pin is referenced to agnd. connect to agnd if not used. 2 4 ovp over voltage protection. this signal is used as redundant ovp protection. this signal is referred to vs - . ep exposed pad. the adp1051 has an exposed thermal pad on the underside of the package. for increased reliability of the solder joints and maximum thermal capability, it is recommended that the pad be soldered to the pcb agnd plane.
preliminary technical data adp1051 rev. pra | page 11 of 17 a pplication configura tions figure 4. full bridge converter figure 5 . half bridge converter adum 3223/ adum4223 dc input adp1051 outa outb load agnd res add rtd vcore ctrl cs1 vs- vs+ vdd ovp sda scl syni/flgi sr1 sr2 pg/alt # adp3624/ adp3654 outc outd vf cs2- cs2+ pmbus adum3223/ adum4223 dc input adp1051 outa outb load cs1 vs+ ovp syni/flgi outc outd cs2- cs2+ vs- agnd vdd res add rtd vcore ctrl sda scl pg/alt# pmbus sr2 adp3624/ adp3654 vf sr1
adp1051 preliminary technical data rev. pra | page 12 of 17 figure 6 . active clamp forward converter adum3221 dc input load adp1051 outa outb agnd res add rtd vcore ctrl cs1 vs- vs+ vdd ovp sda scl syni/flgi sr1 sr2 pg/alt# outc outd cs2- cs2+ pmbus adp3624/ adp3654 vf
preliminary technical data adp1051 rev. pra | page 13 of 17 typical performance characteristics figure 7 . vs adc accuracy vs. temperature (from 10% to 90% of fsr) figure 8 . vf adc accuracy vs. temperature (from 10% to 90% of fsr) figure 9 . cs1 adc accuracy vs. temperature (fr om 10% to 90% of fsr) figure 10 . cs2 adc accuracy vs. temperature (from 0 mv to 120 mv) figure 11 . rtd adc accuracy vs. temperature figure 12 . cs1 fast ocp threshold vs. temperature
adp1051 preliminary technical data rev. pra | page 14 of 17 theory of operation the adp1051 is designed as a flexible, easy - to - use, digital power supply controller . the adp1051 integrates the typical functions that are needed to control a power supply such as: ? output voltage sense and feedback ? voltage feed forward control ? digital loop filter compensation ? pwm generation ? current , voltage, and temperature sense ? housekeeping and i 2 c /pmbus interface ? calibration and trimming the main function of controlling the output voltage is performed using the feedback adcs, the digital loop filter, and the pwm block. the feedback adcs use a multipath approach. there is a combination of a high speed, low resolution (fast and coarse) adc and a low speed, high resolution (slow and accurate) adc. the adc outputs combine to form a high speed and high resolution feedback path. loop compensation is implemented using the digital filter. this pid (proportional, integral, derivative) filter is implemented in the digital domain, allowing easy programming of filter characteristics, which is of great value in customizing and debugging designs. the pwm b lock generates up to six programmable pwm outputs for control of fet drivers and synchronous rectification fet drivers. this programmability allows many traditional and specific switching topologies to be realized. conventional power supply housekeeping fe atures, such as remote and local voltage sense and primary side current sense, are included. an extensive set of protections are offered, including overvoltage protection (ovp), over current protection (ocp), over temperature protection (otp), under voltag e protection (uvp), sr reverse current protection (rcp). all these features are programmable through the i 2 c/pmbus interface. this interface is also used for calibrations. other information, such as input current, output current, and fault flags, is also a vailable through this digital bus interface. the internal eeprom can store all programmed values and allows standalone control without a microcontroller. a free, downloadable adp1051 gui is available that provi des all the necessary software to program the adp1051 . to obtain the latest gui software and a user guide, visit http://www.analog.com/digitalpower . the adp1051 operates from a single 3.3v power supply and is specified from - 40c to 125c. figure 13 . functional block diagram rtd pg/alt# sda scl syni/flgi sr2 sr1 outd outc add vcore agnd res pwm engine adc osc digital core vref pmbus 8kb eeprom vs- vs+ ovp cs1 a d c a d c + + - outa outb a d c vf cs2- cs2+ a d c ctrl vdd uvlo ldo 0.25v 1.2v dac + - -
preliminary technical data adp1051 rev. pra | page 15 of 17 outline dimensions figure 14 . 24 - lead 4 x 4 mm lead frame chip - scale package [lfcsp] mechanical package dimensions ordering guide model 1 temperature range package description package option adp10 5 1acpz - rl ? 40 c to +125c 24 - lead lead frame chip scale package [lfcsp_ w q] cp - 24 - 7 adp1051acpz -r7 ? 40c to +125c 24- lead lead frame chip scale package [lfcsp_wq] cp -24-7 adp1051 - 240- evalz adp1051 240 w evaluation board adp1051 dc1 - evalz adp1051 daughter card adp - i2c - usb -z usb to i 2 c adapter 1 z = rohs compliant part.
adp1051 preliminary technical data rev. pra | page 16 of 17 notes
preliminary technical data adp1051 rev. pra | page 17 of 17 notes ? 20 13 analog devices, inc. all rights reserved. trademarks and registered trademarks are the property of their respective owners. pr1433 - 0 - 3/13/(pra)

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